AP210-based PCB Stackup Design and Warpage Analysis
National Institute of Standards and Technology
Printed circuit boards (PCBs) are multi-material structures that are one of the backbones of the electronics industry. As their performance requirements and complexities increase, the need also increases to better manage factors including warpage, impedance control, and plated through-hole reliability.
The design and specification of PCB stackup (i.e., details about the z-direction PCB cross-section) is a key aspect that influences such factors. However, this kind of design and fabrication knowledge spans multiple disciplines and often multiple organizations (e.g., the PCA/B design organization and the PCB fabricator organization). Proper capture and management of such knowledge in a dynamic market-driven environment is often a challenge.
This project phase will demonstrate how such stackup information can be managed using the AP210 standard (ISO 10303-210) and how it can be used for basic warpage analysis. This effort will also develop a research & development roadmap to achieve fully capable PCB and PCA warpage analysis within standards-based engineering frameworks (including considerations for related physical behaviors and potential application to other types of electronic products such as chip packages).
Future phases are anticipated that will implement this roadmap and include collaboration with relevant types of organizations.
Benefits anticipated from implementing this roadmap include better designs (increased yields and decreased cost and time) and better design knowledge capture (for usage during design, manufacture, and support, as well as for long term archiving).
The proposed effort will be part of the National Institute of Standards and Technology (NIST) Infrastructure for Integrated Electronic Design and Manufacturing (IIEDM) project to provide an environment in which small manufactures of mechanical and electronic components may competitively participate in virtual enterprises that manufacture printed circuit assemblies and boards (PCA/PCB).
Zwemer, D., Bajaj, M., Peak, R., Thurman, T., Brady, K., McCarron, S., Spradling, A., Klein, L., Dickerson, M., Liutkus, G., Messina, J., (May 10-12, 2004).PWB Warpage Analysis and Verification Using an AP210 Standards-based Engineering Framework and Shadow Moiré . EuroSimE 2004 (www.eurosime.com), Brussels, Belgium.
Design-analysis integration (DAI) research.