Andrew J. Scholand Title: DOE Integrated Manufacturing Fellow Status: Graduate Student in Mechanical Engineering Office: Room 215, Manufacturing Research Center Phone: W: (404) 894-8498 , H: (770) 427-5025 Fax: W: (404) 894-9342 E-mail: gt0540b@cad.gatech.edu Education M.S. 1991, Electrical Engineering, Kings College London B.S. 1989, Mechanical Engineering, Worcester Polytechnic Institute Research Interests I'm interested in applying new computer technologies (such as evolutionary computing, distributed computing, XML, and expert systems) to multidisciplinary engineering problems, especially those found in the design and assembly of microelectronic systems. Selected Publications [1] Peak, R. S.; Scholand, A. J; Fulton, R. E. (1996) "On the Routinization of Analysis for Physical Design," Application of CAE/CAD to Electronic Systems, EEP-Vol.18, Agonafar, D., et al., eds., 1996 ASME Intl. Mech. Engr. Congress & Expo., Atlanta, 73-82. [2] Scholand A. J., Bras B., and Fulton R. E. (1999)<"an Investigation Of PWB Layout By Genetic Algorithms To Maximize Fatigue Life," ASME Journal of Electronic Packaging, Volume 121, No. 1, pp. 31 - 36. Go to complete list of GT EIS Lab Publications Personal Home Page Resume