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Manas Bajaj

 

photo

Title:

 Graduate Research Assistant

Status:

 PhD Candidate, Mechanical Engineering

Office:

 MARC 267

Phone:

 +1-404-385-1674

Fax:

 +1-404-894-9342

Address:

 Engineering Information Systems Lab
 267, Manufacturing Research Center
 Georgia Institute of Technology
 813 Ferst Drive, Atlanta, GA 30332, USA

E-mail:

 manas dot bajaj at gatech.edu

Education

 PhD

2008 (expected), Mechanical Engineering,
Georgia Institute of Technology, Atlanta, USA

 

 M.S.

2003, Mechanical Engineering,
Georgia Institute of Technology, Atlanta, USA

 B.Tech.

2001, Ocean Engineering and Naval Architecture,
Indian Institute of Technology, Kharagpur, India

Research Interests

Broadly, my research interests are in the realm of engineering product and systems lifecycle management. Specifically, I am excited about research opportunities in simulation-based design, engineering knowledge representation and information modeling, and open standards-based engineering frameworks. Some specific projects I have been involved with in the past few years are:

 

Capturing Design Process Information and Rationale to Support Knowledge-Based Design-Analysis Integration

NIST and Georgia Tech

http://www.eislab.gatech.edu/projects/nist-dai/

 

AP210-based PCB Stackup Design and Warpage Analysis

NIST and Georgia Tech

http://www.eislab.gatech.edu/projects/nist-warpage/

 

Information Technology and Knowledge-Based Engineering for Enhanced Electronics Manufacturing

Rockwell Collins and Georgia Tech

http://www.eislab.gatech.edu/projects/rci-sfm/

 

The Composable Object (COB) Knowledge Representation: Enabling Advanced Collaborative Engineering Environments (CEEs)

NASA GSFC, NASA JPL, Lockheed Martin and Georgia Tech

http://www.eislab.gatech.edu/projects/nasa-ngcobs/

 

Semantic Framework for Distributed Simulation

Sandia National Labs and Georgia Tech

 

Development of Advanced Collaborative Engineering Environments (CEEs)

NASA JPL and Georgia Tech

http://www.eislab.gatech.edu/projects/nasa-jpl-cee/

 

Research, Development, and Implementation of Next-Generation Engineering Frameworks Institute of Scientific Research and Georgia Tech

http://www.eislab.gatech.edu/projects/nasa-isr-gisstr/

 

Keywords: Simulation-based design, Computer-aided engineering, Product/Systems lifecycle management, Modeling and simulation, Open standards, Information and knowledge representation

 

Doctoral Research

ABSTRACT

 

A Knowledge Composition Methodology for Efficient Analysis Problem Formulation in Simulation-based Design

 

In simulation-based design, a key challenge is to formulate and solve analysis problems efficiently to evaluate a large variety of design alternatives. The solution of analysis problems has tremendously benefited from advancements in commercial off-the-shelf mathematical solvers and computational capabilities. However, the formulation of analysis problems (realized as models) for a given set of design alternatives is a laborious and costly process. In the scope of design alternatives with variable topology multi-body (VTMB) characteristics, this research shall answer the following primary question:

 

How can we improve the efficiency of the analysis model formulation process for VTMB problems?

 

To achieve this, a Composable knowledge methodology is proposed in this research. The fundamental premise of this methodology is to formalize: (a) the idealization knowledge, used in creating analysis models, as modular, reusable, analyst-intelligible, building blocks; (b) the analysis model as a composed system of these building blocks; and (c) a model transformation process using which an analyst may automatically create the analysis model (composed system) from the design model.

 

The envisioned impact of this methodology is to provide a systems-oriented, time- and cost-effective, foundational approach for analysis problem formulation.

 

Please refer to the following papers in the list of publications below for more details.

 

Bajaj, M., Peak, R.S. and Paredis, C.J.J. (2007). Knowledge Composition for Efficient Analysis Problem Formulation, Part 1: Motivation and Requirements.

 

Bajaj, M., Peak, R.S. and Paredis, C.J.J. (2007). Knowledge Composition for Efficient Analysis Problem Formulation, Part 2: Approach and Analysis Meta-Model.

Awards and Achievements

Robert E. Fulton Best Paper Award, Engineering Information Management Track, ASME International DETC/CIE 2005, Long Beach, CA, USA

 

Best Paper Award, Session 210, IEMT Semicon West 2003 conference,
San Jose, CA, USA

 

Elected for Who’s Who Among Students in American Colleges and Universities, 2005 and 2006

 

Best Project Award, 2001, Department of Ocean Engineering & Naval Architecture, Indian Institute of Technology, Kharagpur, India.

 

President’s Silver Medal for 1st ranked undergraduate student (1997-2001), Department of Ocean Engineering and Naval Architecture, Indian Institute of Technology, Kharagpur, India.

 

Dr. J.C. Ghosh Memorial Award for the most outstanding student, 2001, Department of Ocean Engineering & Naval Architecture,
Indian Institute of Technology, Kharagpur, India.

 

Lloyds Register of Shipping (UK) Scholarship for the 1st ranked undergraduate student, 2000-2001, Department of Ocean Engineering & Naval Architecture, Indian Institute of Technology, Kharagpur, India.

 

The J.N. Tata Endowment Award for pursuing graduate studies, 2001, Mumbai, India.

Tools

I am actively involved in developing algorithms and tools as test beds for concepts and methodologies developed during research. Some of these tools are:

 

§   Production Tools (including early R&D prototypes)

 

o  XaiTools PWA-BTM for thermo-mechanical warpage analysis and stackup design of printed circuit boards (being incorporated into XaiTools ElectronicsTM)

 

o  XaiTools ElectronicsTM for modeling and simulation of electronics artifacts — currently incorporates XaiTools PWA-BTM for warpage analysis of PCBs and PCAs; work-in-progress to incorporate XaiTools Chip PackageTM for thermal and thermo-mechanical analyses of chip packages

 

o  SFM DFM Framework a rule-based expert system for design-for-manufacturability evaluation of electronics products

 

§   Research Prototypes

 

o  Semantic Technology plugin for Protégé ontology editor for automated creation of ontologies for distributed federated simulations

Publications (chronological)

§   Bajaj, M., Peak, R.S. and Paredis, C.J.J. (2007). Knowledge Composition for Efficient Analysis Problem Formulation, Part 1: Motivation and Requirements. ASME International Design Engineering Technical Conferences & Computers and Information in Engineering Conference, Las Vegas, NV, USA September 4-7, 2007.

 

§   Bajaj, M., Peak, R.S. and Paredis, C.J.J. (2007). Knowledge Composition for Efficient Analysis Problem Formulation, Part 2: Approach and Analysis Meta-Model. ASME International Design Engineering Technical Conferences & Computers and Information in Engineering Conference, Las Vegas, NV, USA September 4-7, 2007.

 

§   Peak, R.S., Burkhart, R., Friedenthal, S., Wilson, M.W., Bajaj, M. and Kim, I. (2007). Simulation-Based Design Using SysML, Part 1: A Parametrics Primer. INCOSE International Symposium, San Diego, CA, USA June 24-28, 2007.

 

§   Peak, R.S., Burkhart, R., Friedenthal, S., Wilson, M.W., Bajaj, M. and Kim, I. (2007). Simulation-Based Design Using SysML, Part 2: Celebrating Diversity by Example. INCOSE International Symposium, San Diego, CA, USA June 24-28, 2007.

               

§   Bajaj, M., Peak, R., Zwemer, D., Thurman, T., Klein, L., Liutkus, G., Brady, K., Messina, J. and Dickerson, M. (2006). Automating Thermo-Mechanical Warpage Estimation of PCBs/PCAs Using a Design-Analysis Integration Framework. Mentor U2U, San Jose, CA, USA May 3-5, 2006.

 

§   Klein, L., Peak, R., Thurman, T., Smith, G., Waterbury, S. and Bajaj, M. (2006). Standards-based Environment for Electro-Mechanical Product Realization. Mentor U2U, San Jose, CA, USA May 3-5, 2006.

 

§   Bajaj, M., Paredis, C., Rathnam, T. and Peak, R. (2005). Federated Product Models for Enabling Simulation-based PLM. ASME International Mechanical Engineering Congress and Exposition (IMECE), Orlando, FL, USA Nov 5-11, 2005.

 

§   Bajaj, M., Kim, I., Mocko, G., Peak, R., Udoyen, N., Wilson, M., Greene, D., Raines, B. and Srinivasan, V. (2005). Diagnosing Engineering Information Interoperability, Recognizing the value of standards-based PLM – Part 1. ASME DETC / CIE, Long Beach, CA, USA September 24-28, 2005.

 

§   Kim, I., Bajaj, M., Udoyen, N., Mocko, G., Peak, R. and Wilson, M. (2005). Metrics for Degree-of-Openness of Engineering Information, Recognizing the value of standards-based PLM - Part 2, Recipient of the Robert E. Fulton Best Paper Award. ASME DETC/CIE, Long Beach, CA, USA September 24-28, 2005.

 

§   Bajaj, M., Peak, R., Klein, L., Dickerson, M. and Zwemer, D. (2005). Standards-based Engineering Frameworks for Next-Generation PLM. PLM World, Dallas, TX, USA May 2-6, 2005.

 

§   Bajaj, M., Peak, R., Zwemer, D., Thurman, T., Dickerson, M., Brady, K. and Messina, J. (2005). Next Generation Simulation-based Design Technologies for Electronics Product Realization. The 7th NASA-ESA Workshop on Product Data Exchange (PDE), MARC, Georgia Tech, Atlanta, GA, USA April 19-22, 2005.

 

§   Bajaj, M., Paredis, C., Rathnam, T. and Peak, R. (2005). Federated Product Models for Simulation-based PLM. The 7th NASA-ESA Workshop on Product Data Exchange (PDE), MARC, Georgia Tech, Atlanta, USA April 19-22, 2005.

 

§   Peak, R., Friedenthal, S., Moore, A., Burkhart, R., Waterbury, S., Bajaj, M. and Kim, I. (2005). Experiences Using SysML Parametrics to Represent Constrained Object-based Analysis Templates. 7th NASA-ESA Workshop on Product Data Exchange (PDE), Atlanta, GA, USA May 2-6, 2005.

 

§   Zwemer, D., Bajaj, M., Peak, R., Klein, L. and Dickerson, M. (2005). Standards-based Engineering Frameworks for Next-Generation PLM. The 7th NASA-ESA Workshop on Product Data Exchange (PDE), Atlanta, GA, USA April 19-22, 2005.

 

§   Zwemer, D., Bajaj, M., Peak, R., Thurman, T., Brady, K., McCarron, S., Spradling, A., Dickerson, M., Klein, L., Liutkus, G. and Messina, J. (2004). PWB Warpage Analysis and Verification Using an AP210 Standards-based Engineering Framework and Shadow Moiré. IEEE EuroSimE, Brussels, Belgium May 10-12, 2004.

 

§   Bajaj, M., Peak, R., Wilson, M., Kim, I., Thurman, T., Benda, M., M.C.Jothishankar, Ferreira, P.M. and Stori, J. (2003). Towards Next-Generation Design-for-Manufacturability (DFM) Frameworks for Electronics Product Realization, Recipient of the Best Paper Award for Session 210. IEMT Semicon West, San Jose, CA, USA July 16-18, 2003.

 

§   Bajaj, M., Peak, R. and Fulton, R.E. (2003). Customizing Next-Generation Multidisciplinary Product Realization Frameworks. ASME International DETC/CIE, Chicago, IL Sep 2-6, 2003.

 

§   Peak, R., Bajaj, M., Wilson, M., Kim, I., Thurman, T., M.C.Jothishankar, Ferreira, P., Stori, J., Mukhopadhyay, D., Tang, D., Liutkus, G. and Klein, L. (2003) Enhancing Design-for-Manufacturability Using the ISO 10303 Standard for Electronics Design: AP210. Aerospace Product Data Exchange (APDE) Workshop, NIST, Gaithersburg, MD, USA April 7-10, 2003.

 

§   Matsuki, R., Peak, R., Zeng, S., Wilson, M., Kim, I. and Bajaj, M. (2002). Design-Analysis (Thermal and Mechanical) Integration Research for Electronic Packaging. Semicon Japan 2002, Japan.

 

§   Peak, R., Wilson, M., Kim, I., Udoyen, N., Bajaj, M., Mocko, G., Liutkus, G., Klein, L. and Dickerson, M. (2002). Creating Gap-Filling Applications Using STEP Express, XML, and SVG-based Smart Figures - An Avionics Example. NASA-ESA Workshop on Aerospace Product Data Exchange, ESA/ESTEC, Noordwijk (ZH), The Netherlands April 9-12, 2002.

Reports & Whitepapers

§       Peak, R. and Bajaj, M. (2007). Capturing Design Process Information and Rationale to Support Knowledge-Based Design and Analysis Integration, NIST-Georgia Tech Design-Analysis Integration Project (Phase 3). Atlanta, GA, USA, Georgia Tech.

 

§       Peak, R., Bajaj, M., Kim, I. and Mocko, G. (2006). Capturing Design Process Information and Rationale to Support Knowledge-Based Design and Analysis Integration, NIST-Georgia Tech Design-Analysis Integration Project (Phase 2). Atlanta, GA, USA, Georgia Tech.

 

§   Peak, R., Mocko, G., Bajaj, M. and Kim, I. (2004). Capturing Design Process Information and Rationale to Support Knowledge-Based Design and Analysis Integration, NIST-Georgia Tech Design-Analysis Integration Project (Phase 1). Atlanta, GA, USA, Georgia Tech.

 

§   Bajaj, M., Mocko, G., Kim, I., Udoyen, N., Wilson, M., Peak, R., Paredis, C., Greene, D., Srinivasan, V. and Raines, B. (2004). GT-Diagnostics: Recognizing the value of standards-based PLM systems. Atlanta, GA, USA, Georgia Tech and IBM.

Curriculum Vitae

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