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Design-Analysis Integration Research for Electronic Packaging

Sponsor

Shinko Electric Industries Co., Ltd. - Nagano, Japan

Phase 1 (1999-2000)

Simulating the behavior of electronic chip packages like ball grid arrays (BGAs) is important to guide and verify their designs.  Thermal resistance, thermomechanical stress, and electromagnetics impose some of the main challenges that package designers need to address.  Yet because packages are composed of numerous materials and complex shapes, with current methods an analyst may spend hours to days creating simulations like finite element analysis (FEA) models.

This paper overviews work to reduce design cycle time by automating key aspects of FEA modeling and results documentation.  The main objective has been automating FEA-based thermal resistance model creation for a variety of package styles: quad flat packs (QFPs), plastic BGAs (PBGAs), and enhanced BGAs (EBGAs).  Pilot production tools embody analysis integration techniques that leverage rich product models and idealize them into FEA models.  We have also demonstrated how the same rich product models can drive basic stress models with different idealizations.

In this framework, Internet standards like CORBA enable worldwide access to simulation solvers (e.g., Ansys and Mathematica).  Automation and ease-of-use enable access by chip package designers and others who are not simulation specialists.  Pilot industrial usage has shown that total simulation cycle time can be decreased 75%, while modeling time itself can be reduced 10:1 or more (from hours to minutes). 

Phase 2: Enhancing Thermal Resistance Analysis Capabilities (2001-2002)

Phase 1 achieved automated analysis capabilities for the thermal resistance of several chip package families.  With these tools, Shinko performed numerous test cases and achieved more than 75% reduction in total simulation process time in initial production usage.  Phase 2 enhances insertion these capabilities into full production usage for a broader Shinko user base.  It also develops techniques that perform automated product information-driven analysis for a wider range of thermal resistance analysis modules.

References

Russell S. Peak, Ryuichi Matsuki, Miyako W. Wilson, Donald Koo, Andrew J. Scholand, Yukari Hatcho, Sai Zeng (July, 2001) An Object-Oriented Internet-based Framework for Chip Package Thermal and Stress Simulation. InterPACK'01, Hawaii.