An Information-Driven FEA Model Generation Approach for Chip Package Applications
Zeng S., Peak R., Matsuki R., Xiao A., Wilson M., Fulton R. E.(2003) An Information-Driven FEA Model Generation Approach for Chip Package Applications, ASME, 23rd Computers and Information in Engineering Conference, September 2-6, Chicago, Illinois.
Multi-Representation Architecture (MRA), Analysis Building Block (ABB), Ready to Mesh Model (RMM), Solution Method Model (SMM), Constrained Object (COB), Variable Topology Multi-Body (VTMB), Finite Element Analysis (FEA), and Design Analysis Integration
In the electronic chip package development process, Finite Element Analysis (FEA) modeling is widely used as a virtual prototyping technology to achieve good designs.Due to the complexity and variability in materials, geometric shapes, and connectivity configurations, etc. in a chip package, FEA modeling is a tedious and time-consuming activity.Typically finite element modeling takes hours or even days to complete an analysis for a single chip package design. The Multi-Representation Architecture (MRA) is presented as a framework to facilitate automatic transformations of design models into analysis models through four stepping-stone information representations: (1) analyzable product models (APM), (2) context-based analysis models (CBAM), (3) analysis building blocks (ABBs), and (4) solution method models (SMMs). The ABB models describe theoretical physical systems while SMMs represent the ABB models in solution technique-specific form, such as FEA.
In this paper, we present an information-driven FEA modeling approach facilitating the mapping between ABBs and SMMs by first decomposing the geometry into meshable bodies and subsequently generating vendor-specific SMMs. To demonstrate this FEA modeling approach, a chip package thermomechanical analysis example is given. The information-driven FEA modeling approach is shown to be an effective and efficient method for capturing engineering information in chip package products, as well as decreasing FEA modeling time.
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