PWB Warpage Analysis and Verification Using an AP210 Standards-based Engineering Framework and Shadow Moiré Reference Zwemer, D., Bajaj, M., Peak, R., Thurman, T., Brady, K., McCarron, S., Spradling, A., Klein, L., Dickerson, M., Liutkus, G., Messina, J., (May 10-12, 2004). PWB Warpage Analysis and Verification Using an AP210 Standards-based Engineering Framework and Shadow Moiré. EuroSimE 2004 (www.eurosime.com), Brussels, Belgium Keywords PWB / circuit board warpage analysis, stackup, standards-based framework, AP210, STEP, multi-representation architecture, shadow Moiré, phase stepping Abstract Thermally induced warpage of printed wiring boards (PWB) and printed wiring assemblies (PWAs) is an increasingly important issue in managing the manufacturing yield and reliability of electronic devices. In this paper, we introduce complementary simulation and experimental verification procedures capable of investigating warpage at the local feature level as well as the global PWB level. Simulation within a standards-based engineering framework allows efficient introduction of detailed feature information into warpage models of varying fidelity. Experimental results derived from temperature-dependent shadow moiré provide a rapid high resolution picture of local warpage in critical regions. We describe initial results for two unpopulated PWB test cases which indicate a promising outlook for the methodology. Documents Manuscript: pdf Presentation: ppt See Also ... Project web page